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[Other resource] VerilogHDLshejifengpingqihe32weijishuqi

Description: 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
Platform: | Size: 159000 | Author: 少华 | Hits:

[VHDL-FPGA-Verilog] Verilog_FPGA_fp

Description: 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
Platform: | Size: 124928 | Author: xiong | Hits:

[Software Engineering] VerilogHDLshejifengpingqihe32weijishuqi

Description: 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
Platform: | Size: 158720 | Author: 少华 | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] clkdiv

Description: 占空比可调 分频系数 都可随意设定的分频器，语言为Verilog HDL-Duty cycle factor can be freely adjustable frequency divider set the language for the Verilog HDL
Platform: | Size: 1024 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] verilog_std_div

Description: Verilog HDL语言实现任意整数分频.只需调节分频数和分频位宽即可。-Verilog HDL language to any integer divider. Simply adjust the number and frequency can be frequency division-bit wide.
Platform: | Size: 253952 | Author: zhouming | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog HDL 1.红外线发射调制电路 2.分数分频 3.最大公约数和最小公倍数 4.秒表-1.infra transmission modulator 2.fractal frequency divider 3.maximal common divisor 4.timer
Platform: | Size: 11264 | Author: 黄甦 | Hits:

[VHDL-FPGA-Verilog] div_frequency

Description: 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
Platform: | Size: 1024 | Author: ye | Hits:

[VHDL-FPGA-Verilog] frequency-divider

Description: 用VERILOG 语言写的数控分频器，可能输入时钟信号实现任意整数倍的分频，-NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
Platform: | Size: 491520 | Author: zyb | Hits:

[OS program] Divider

Description: 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
Platform: | Size: 103424 | Author: wmy36 | Hits:

[VHDL-FPGA-Verilog] frequency divider and testbench

Description: a frequency divider and test bench with simulation results
Platform: | Size: 493568 | Author: abitofhero | Hits:

[VHDL-FPGA-Verilog] y1

Description: FPGA input clock frequency 50Mhz, try to design a frequency divider to realize 1Hz count signal. Requirements: writing design modules; Write the test model.
Platform: | Size: 21963776 | Author: pluss | Hits:

[VHDL-FPGA-Verilog] jiaotongdeng_fuza

Description: 本文基于FPGA技术的发展和Quartus II开发平台，实现路口交通灯控制器是一种解决方案。使用Verilog HDL硬件描述语言来描述语言程序的分频器模块，控制模块，数据解析模块，显示译码模块和段选位选模块，五个模块，并通过各个模块程序之间的端口合理连接和协调，成功设计出交通信号灯控制电路。在Quartus II环境下模拟，生成顶层文件下载后，在FPGA EP2C5Q208器件进行验证。(Based on the development of FPGA technology and the development platform of Quartus II, the realization of traffic lights controller at intersection is a solution. The Verilog HDL hardware description language is used to describe the frequency divider module of the language program, the control module, the data parsing module, the decoding module and the segment selection and selection module, five modules, and the communication and communication light control circuit is successfully designed through the reasonable connection and coordination of the ports between each module program. In the Quartus II environment, the simulation generates top-level files after downloading in FPGA The EP2C5Q208 device is verified.)
Platform: | Size: 5611520 | Author: 威威谈谈 | Hits:

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